A liquid crystal display device is recently applied to various kinds of electric appliances as a thin and light flat panel display which can be driven at a low voltage and a low power, and the electric appliances are widely sold. As such liquid crystal display device, a matrix type liquid crystal display device is known.
The matrix type liquid crystal display device is such that an optical characteristic of liquid crystal is varied by applying driving voltages respectively applied to picture elements disposed in a matrix manner so as to display images and letters. Particularly, an active matrix driving mode enables high quality display such as high contrast and high speed response since it has a switching element such as a TFT (Thin Film Transistor) and a MIM (Metal Insulator Metal) in each picture element.
Here, description is given on an arrangement of the active matrix type liquid crystal display device using the TFT element.
The active matrix type display device includes a pair of upper and lower glass substrates, and liquid crystal is sealed therebetween. The one substrate is provided with the TFT element and a circuit wire connected to the TFT element.
That is, as shown in FIG. 9, on the substrate, there are provided scanning wires 81 (G1, G2, . . . ) from a scanning wire driving circuit 83 and signal wires 82 (S1, S2, . . . ) from a signal wire driving circuit 84 so that they are orthogonal to each other. In the vicinity of each of intersections of the scanning wires 81 (G1, G2, . . . ) and the signal wires 82 (S1, S2, . . . ), a TFT 85 is provided, and the TFT 85 is connected to a transparent pixel electrode 90.
Further, as shown in FIG. 10, a common electrode 92 is provided opposite to the pixel electrode 90, and the common electrode 92 is connected to a common wire (not shown). The pixel electrode 90 and the common electrode 92 constitute a capacitor for securing a crystal liquid capacitance Clc 91.
While, a gate electrode 87 of the TFT 85 is connected to each of the scanning wires 81 (G1, G2, . . . ), and a source electrode 88 of the TFT 85 is connected to each of the signal wires 82 (S1, S2, . . . ), and a drain electrode 89 of the TFT 85 is connected to the pixel electrode 90. Further, there is provided an auxiliary capacitance wire 86 below the pixel electrode 90. In order to realize the high image quality by improving retention of the liquid crystal, the pixel electrode 90 and the auxiliary capacitance wire 86 constitute a capacitor for securing auxiliary capacitance Cs 93.
In the arrangement, when the scanning wire driving circuit 83 inputs scanning signals to the scanning wires 81 (G1, G2, . . . ) sequentially, the input of the scanning signals allows gates of the TFTs 85 in one row to be ON simultaneously, and the signal wire driving circuit 84 inputs display data signals from the signal wires 82 (S1, S2, . . . ) to the respective pixels.
Thus, each of the data signals is applied to the pixel electrode 90, and a potential difference between the pixel electrode 90 and the common electrode 92 varies transmittance of the liquid crystal, so that letters and images are displayed on a liquid crystal panel. However, in this case, when a dc voltage is applied to the liquid crystal for a long time, a retaining property of the liquid crystal deteriorates. Thus, the polarity of the data signals inputted to the signal wires 82 (S1, S2, . . . ) is inverted at each horizontal period, for example, so as to perform so-called ac driving so that a positive voltage and a negative voltage are alternately applied to the pixel electrode 90.
Incidentally, in a case where conductive films are disposed in parallel or the conductive films are disposed up and down with an insulating film therebetween, it is general that there occurs parasitic capacitance therebetween. That is, an ideal condition of each pixel is such that, as shown in FIG. 10, there exist merely (a) the liquid crystal capacitance Clc 91 between the pixel electrode 90 and the common electrode 92 and (b) the auxiliary capacitance Cs 93 between the pixel electrode 90 and the auxiliary capacitance wire 86.
Here, description is given by focusing on one pixel in the second row and in the second column shown in FIG. 9 for example, that is, a pixel in which the gate of the TFT 85 is connected to the scanning wire G2 positioned at the second stage from the top and the source of the TFT 85 is connected to the signal wire S2 positioned at the second stage from the left in FIG. 9.
As shown in FIG. 9, the pixel is such that the pixel electrode 90 is surrounded by the upper and lower scanning wires G2 and G3 and the left and right signal wires S2 and S3. Thus, as shown in FIG. 11, there occur the parasitic capacitance Cgd 94, Cgd 97, Csd 95, and Csd 96 between the pixel electrode 90 and the wires G2, G3, S2, and S3.
Further, in a case where the pixel electrode 90 is made to overlap the scanning wire 81 and/or the signal wire 82 with the insulating layer therebetween so as to increase an aperture ratio of the picture element, there occurs parasitic capacitance 98 between the pixel electrodes 90 adjacent to each other. Thus, a potential of the drain electrode 89 is influenced by the coupling of other capacitance and the parasitic capacitance brought about between the drain electrode 89 and the all the peripheral wires.
However, the conventional liquid crystal display device brings about the following problems.
That is, the foregoing description on the case where the parasitic capacitance occurs in each pixel is to illustrate one pixel in which the TFT 85 is connected to the signal wire S2 at the second stage from the right. When description is given by focusing on one pixel in which the TFT 85 is connected to the leftmost signal wire S1, the pixel electrode 90 does not exist leftward with respect to the pixel electrode 90 constituting the pixel, so that the parasitic capacitance 98 does not occur between the pixel electrode 90 and the left pixel electrode 90.
Further, when the signal wire S1 is focused on, no pixel exists leftward with respect to the signal wire S1, so that there is no parasitic capacitance Csd 96 between the signal wire S1 and the left pixel electrode 90. Merely the parasitic capacitance Csd 95 exists between the pixel electrodes 90 adjacent to each other, so that wire capacitance in the signal wire S1 is smaller than that of the signal wires S2 and S3 centrally disposed.
Thus, the leftmost signal wire Si is different from the signal wires S2, S3, that are centrally positioned, and they are different from each other in the coupling capacitance of the wiring and the pixels. Thus, under the same driving condition as in the signal wires S2, S3, . . . , the drain electrode 89 of the pixel in the signal wire S1 has a potential different from that of the pixels centrally disposed.
Thus, even when the same voltages are to be applied to all the pixels of the entire screen, a different voltage is applied to the liquid crystal of the left-end pixel unlike the pixels centrally positioned, so that there occurs such a problem that the leftmost pixel is seemingly colored when a gray image is displayed.
Note that, the foregoing description is on the leftmost signal wire S1, and the rightmost signal wire Sn bears the same problem since the capacitive condition is different from that of the central lines.
Note that, as a solution for this problem, Japanese Unexamined Patent Publication No. 84239/1995 (Tokukaihei 7-84239) (Publication date: Mar. 31, 1995) discloses a liquid crystal display device. In this technique, a dummy signal wire is provided adjacent to the signal wire, but the following problem remains to be solved. In a case where the pixel electrode is made to overlap the scanning wire and/or the signal wire with the insulating layer therebetween so as to increase an aperture ratio of the picture element, the parasitic capacitance between the pixel electrodes adjacent to each other exerts bad influences.